Implementation and self-checking of different adder circuits

The function of addition in arithmetic unit that can be used in complement operations, encoding and decoding [1]. It can be implemented in different arrangement or using different basic logic gates with different bits and become different type of adders. Basically, all types of the complex adder circuits are made up from the simple adder circuits (or called basic building blocks of adder) like half adder and full adder

Design of Complex Multiplier Using Vedic Mathematics

In this project, a 4x4 multiplier is implemented that utilizes the Urdhava Tiryakbhyam sutra method in Vedic mathematics. This method is applicable in all two decimal number multiplications which offers high speed calculation and improved efficiency. Thus, the design of a 4x4 Vedic-based multiplier is solely aimed at performing faster multiplications and achieving quicker processing speeds than the traditional multipliers. The architecture of the Vedic multiplier consists of four 2x2 multipliers and three adders of different bit sizes that are assembled using the Wallace tree implementation. The coding for the multipliers and adders is written in Verilog Hardware Description Language (HDL) in the Quartus Prime 17 Software. Functional simulation is then carried out to ensure that the Vedic multiplier performs the accurate multiplication operations, while the Verilog Compiled Simulator is employed to compile and simulate the multiplier design. Following this, the Design Compiler (DC) and Integrated Circuit Compiler (ICC) command scripts are then composed to allow the logic and physical synthesis to be performed on the Vedic and traditional multipliers. From there, the performance level of both these multipliers are assessed through reference to several key parameters such as timing, area, power consumption, overflow percentage and congestion statistics. Based on the results obtained in the synthesis process, the Vedic multiplier possesses faster operational speed than the traditional multiplier (due to a shorter processing time), but ultimately exhibits a greater power consumption and wider area coverage. &nbsp

Design of Complex Multiplier Using Vedic Mathematics

In this project, a 4x4 multiplier is implemented that utilizes the Urdhava Tiryakbhyam sutra method in Vedic mathematics. This method is applicable in all two decimal number multiplications which offers high speed calculation and improved efficiency. Thus, the design of a 4x4 Vedic-based multiplier is solely aimed at performing faster multiplications and achieving quicker processing speeds than the traditional multipliers. The architecture of the Vedic multiplier consists of four 2x2 multipliers and three adders of different bit sizes that are assembled using the Wallace tree implementation. The coding for the multipliers and adders is written in Verilog Hardware Description Language (HDL) in the Quartus Prime 17 Software. Functional simulation is then carried out to ensure that the Vedic multiplier performs the accurate multiplication operations, while the Verilog Compiled Simulator is employed to compile and simulate the multiplier design. Following this, the Design Compiler (DC) and Integrated Circuit Compiler (ICC) command scripts are then composed to allow the logic and physical synthesis to be performed on the Vedic and traditional multipliers. From there, the performance level of both these multipliers are assessed through reference to several key parameters such as timing, area, power consumption, overflow percentage and congestion statistics. Based on the results obtained in the synthesis process, the Vedic multiplier possesses faster operational speed than the traditional multiplier (due to a shorter processing time), but ultimately exhibits a greater power consumption and wider area coverage. &nbsp

Test Scheduling of SoC by using Dynamic Voltage Frequency Scaling (DVFS) Technique

High temperature gradients in System on Chip (SoC) lowered the performances, reliability and leakage power. In addition, temperature during testing gain more compared to normal operation. Therefore, the investigation of the impact dynamic voltage frequency scaling (DVFS) on the thermal aware test scheduling performance will be the main contribution of this work. The test scheduling algorithm which embeds frequency scaling effect with dynamic voltage supply is tested on ITC’02 benchmark. The formulation of ILP is to minimize the group of the test session in SoC and continued with DVFS formulation. Compared to the conventional thermal-aware scheduling approach based purely on a frequency scaling, this technique provides shorter overall test times and greatly improved flexibility to satisfy strict thermal constraints. The proposed DVFS with thermal aware task scheduling allows to minimize test time more than 46%

Meletakkan tarikh berlaku kiamat adalah khurafat

Maklumat diperoleh daripada papan web (webbot) meramalkan akan berlaku perang nuklear pada 2008 atau 2009. Kini Korea Utara sedang giat melancarkan ujian peluru berpandu dan senjata nuklear, tindakan itu mendapat bantahan banyak negara

Nisbah pelajar, pensyarah perubatan mesti dipertahankan

Tidak dinafikan profesion perubatan, terutama di hospital atau pusat perubatan swasta menjanjikan tawaran lumayan. Namun, ramai pensyarah melupakan tarikan itu semata-mata untuk mengajar dan menjadikan anak bangsa seorang doktor bagi memenuhi keperluan rakyat dan negara

Makmal Institut Halal Malaysia tingkat imej negara.

PEMBINAAN Makmal Institut Halal Malaysia bakal membawa jenama halal Malaysia maju selangkah lagi sekaligus meningkatkan imej negara yang memang diiktiraf serta menjadi contoh dalam industri halal global

A study on the effect of oral hypoglycaemic agents on arterial stiffness among malay patients with type 2 diabetes mellitus

Objective : The purpose of this study is to see whether there was any significant difference in arterial stiffness (as measured by augmentation index) between diabetic and non diabetic subjects and to see whether there was any significant difference between two different oral hypoglycaemic agents(OHA) regimens, (sulphonylurea monotherapy and metformin in combination with sulphonylurea therapy) on arterial stiffness. Methods : This was a case control study conducted in the Klinik rawatan keluarga(KRK) and Diabetic clinic, HUSM from May 2004 till May 2005. Hundred and two diabetic subjects and hundred and two age- and sex-matched non-diabetic control subjects were recruited after obtaining verbal consent following explanation of study protocol. Augmentation index (AI) was measured using the Sphygmocor apparatus and all measurements were performed by the researcher after an earlier validation study. These mean augmentation index measurements were then analyzed. Result : The mean of AI of diabetic subjects was significantly higher than non diabetic subjects ( 140.32 ± 12.0% Vs 128.77 ± 10.69%, P < 0.0001 ). However, therewas no significant difference in mean AI between two different OHA regimen groups in diabetic subjects (140.51 ± 11.42 Vs 140.14 ± 12.86, 95% CI: -4.40, 5.15, p = 0.877). Conclusion: Diabetic patients have increased arterial stiffness compared with age- and sex-matched non diabetic subjects, which may partly explain why diabetes mellitus are associated with increased cardiovascular risk. This study also showed that two different groups of oral hypoglycaemic agents have no effect in relation to arterial stiffness